51 Series Micro Controller

The Intel MCS-51 (commonly termed 8051) is a single chip microcontroller (MCU) series developed by Intel in 1980 for use in embedded systems. The architect of the Intel MCS-51 instruction set was John H. Wharton. Intel’s original versions were popular in the 1980s and early 1990s, and enhanced binary compatible derivatives remain popular today. It is a complex instruction set computer with separate memory spaces for program instructions and data.

Intel’s original MCS-51 family was developed using N-type metal–oxide–semiconductor (NMOS) technology, like its predecessor Intel MCS-48, but later versions, identified by a letter C in their name (e.g., 80C51) use complementary metal–oxide–semiconductor (CMOS) technology and consume less power than their NMOS predecessors. This made them more suitable for battery-powered devices.

The family was continued in 1996 with the enhanced 8-bit MCS-151 and the 8/16-bit/32-bit MCS-251 family of binary compatible microcontrollers.[3] While Intel no longer manufactures the MCS-51, MCS-151 and MCS-251 family, enhanced binary compatible derivatives made by numerous vendors remain popular today. Some derivatives integrate a digital signal processor (DSP) or a floating-point unit (coprocessor, FPU). Beyond these physical devices, several companies also offer MCS-51 derivatives as IP cores for use in field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC) designs.

The 8051 architecture provides many functions (central processing unit (CPU), random-access memory (RAM), read-only memory (ROM), input/output (I/O) ports, serial port, interrupt control, timers) in one package:

8-bit arithmetic logic unit (ALU) and accumulator, 8-bit registers (one 16-bit register with special move instructions), 8-bit data bus and 2×16-bit address buses, program counter, data pointer, and related 8/11/16-bit operations; hence it is mainly an 8-bit microcontroller
Boolean processor with 17 instructions, 1-bit accumulator, 32 registers (4 × 8-bit, bit-addressable) and up to 144 special 1 bit-addressable RAM variables (18 × 8-bit)[4]
Multiply, divide and compare instructions
Four fast switchable register banks with eight registers each (memory mapped)
Fast interrupt with optional register bank switching
Interrupts and threads with selectable priority[5]
128 or 256 bytes of on-chip RAM (IRAM)
Dual 16-bit address bus; it can access 2×216 memory locations: 64 KB (65,536 locations) each of ROM (PMEM) and external RAM (XRAM), using two memory buses in a Harvard architecture.
On-chip ROM (not included on 803x variants)
Four (three full) 8-bit bi-directional input/output ports, bit addressable
UART (serial port)
Two 16-bit counter/timers
Power saving mode (on some derivatives)

One feature of the 8051 core is the inclusion of a Boolean processing engine, which allows bit-level Boolean logic operations to be carried out directly and efficiently on select internal registers, ports and select RAM locations. Another feature is the inclusion of four bank selectable working register sets, which greatly reduce the time required to perform the context switches to enter and leave interrupt service routines. With one instruction, the 8051 can switch register banks, avoiding the time-consuming task of transferring the critical registers to RAM.

Once a UART, and a timer if necessary, has been configured, the programmer needs only write a simple interrupt routine to refill the send shift register whenever the last bit is shifted out by the UART and/or empty the full receive shift register (copy the data somewhere else). The main program then performs serial reads and writes simply by reading and writing 8-bit data to stacks.